168

Chapter 29. MIPS Dependent Features

 mgp64

Assume that 64 bit general purpose registers are available. This is provided in the interests of

symmetry with  gp32.

 mips16

 no mips16

Generate code for the MIPS 16 processor. This is equivalent to putting

.set mips16

at the start

of the assembly file.

 no mips16

turns off this option.

 mips3d

 no mips3d

Generate code for the MIPS 3D Application Specific Extension. This tells the assembler to ac 

cept MIPS 3D instructions.

 no mips3d

turns off this option.

 mdmx

 no mdmx

Generate code for the MDMX Application Specific Extension. This tells the assembler to accept

MDMX instructions.

 no mdmx

turns off this option.

 mfix7000

 mno fix7000

Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction

occurs in the following two instructions.

 mfix vr4120

 no mfix vr4120

Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC 

generated code: it is not designed to catch all problems in hand written assembler code.

 m4010

 no m4010

Generate code for the LSI r4010 chip. This tells the assembler to accept the r4010 specific in 

structions (

addciu

,

ffc

, etc.), and to not schedule

nop

instructions around accesses to the

HI

and

LO

registers.

 no m4010

turns off this option.

 m4650

 no m4650

Generate code for the MIPS r4650 chip. This tells the assembler to accept the

mad

and

madu

instruction, and to not schedule

nop

instructions around accesses to the

HI

and

LO

registers.

 no m4650

turns off this option.

 m3900

 no m3900

 m4100

 no m4100

For each option

 mnnnn

, generate code for the MIPS r

nnnn

chip. This tells the assembler to

accept instructions specific to that chip, and to schedule for that chip's hazards.

 march=cpu

Generate code for a particular MIPS cpu. It is exactly equivalent to

 mcpu

, except that there are

more value of

cpu

understood. Valid

cpu

value are: